1. Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating semiconductor devices. More specifically, the invention relates to a method for packaging or encapsulating an integrated circuit (IC) die having conductive bumps or bonds that protrude beyond the IC covering or package.
2. State of the Art
In semiconductor manufacture, a single semiconductor die, chip, or integrated circuit is typically mounted within a sealed package. The package generally protects the die from physical damage and from contaminants, such as moisture or chemicals, found in the surrounding environment. The package also provides a lead system for connecting electrical devices (integrated circuits), formed on the die, to a printed circuit board or other external circuitry.
Semiconductor packages containing integrated circuits for a broad range of purposes are currently mass produced. Measurable savings in the packaging of one such semiconductor die or integrated circuit can generate large overall cost savings, due to large production volumes, if the reduced-cost packaging affords required package integrity. Further, reduction in package size can eliminate size-based restrictions for use of a die on ever more crowded carrier substrates such as printed circuit boards (PCBs), where available "real estate" is at a premium. Therefore, continual cost and quality improvements in the manufacture of these semiconductor packages, while maintaining the overall dimensions of such packages at a reduced size, are of great value in the semiconductor manufacturing field.
In many semiconductor applications, formation of conductive bumps on the bond pads of an IC die is desirable, if not necessary. The most common applications where conductive bumps are used include tape automated bonding (TAB), flip-chip attachment of a die to a carrier substrate, and direct chip attachment (DCA) of a die to a printed circuit board. Formation of the conductive bumps used in these applications can be accomplished using a variety of commonly known methods, such as metal deposition onto bond pads by screening or printing, or ball bumping techniques using wire bonding equipment.
A widely practiced way to increase the number of available input/output (I/O) connections is to use flip-chip methodology for packaging, where an array of contacts (e.g., conductive bumps or balls) is positioned on the active surface or circuit face of the die and the die is mounted circuit face down upon a single chip or multi-chip module carrier.
Because of the high manufacturing costs associated with state-of-the-art metal deposition techniques, many semiconductor manufacturers have resorted to ball bumping processes using standard wire bonding tools to form conductive bumps over the bond pads. In the ball bumping process, a capillary of the wire bonding tool carries a conductive wire toward a bond pad on which a bump is to be formed. A ball is formed at an end of the wire by heating and melting the metal wire. The wire bonding tool capillary then presses the ball against the planar bond pad and the portion of the wire extending past the ball is cut, leaving a ball bump on the bond pad.
A flip-chip or bumped (raised) die is a semiconductor chip (die) having conductive bumps formed on bond pads on the active surface or front side of the die, the conductive bumps being used as electrical and mechanical connectors. The die is inverted (flipped) and bonded to trace ends or other terminals on a carrier substrate by means of the conductive bumps. Several materials are conventionally used to form the conductive bumps on the die, such as solder conductor polymers, and conductor-filled polymers. Typically, if the conductive bumps are solder bumps, the solder bumps are deposited and then reflowed to form a spherical shape, and subsequently re-heated to form a solder joint between the bond pads on the so-called flip-chip and the substrate terminals, the solder joint forming both electrical and mechanical connections between the flip-chip and substrate.
Flip-chip IC devices, formed according to the aforementioned fabrication processes, have a number of shortcomings. For example, since the active surface of the chip is relatively unprotected, being covered only with a thin passivation layer, damage to the chip can occur during attachment of the chip to the PCB. Likewise, such defect to the chip can occur during handling of the chip or while conducting reliability testing of the same.
As disclosed in U.S. Pat. No. 5,496,775 to Brooks, encapsulated IC dice having conductive bumps have been developed in an attempt to solve some of these problems. In the fabrication process of Brooks, gold balls, which function as leads or contacts, are welded in a stacked or tower fashion onto each bond pad of the IC die. The gold ball tower-bonded die is then placed into a mold and onto a first layer of encapsulation material contained therein. A second layer of encapsulation material is then applied over the tower side of the die, which completely covers the die surface, partially submerging the towers in the encapsulant. The encapsulated IC die is removed from the mold and mounted to tab tape or a PCB, with the non-submerged portions of the towers providing an electrical connection thereto. Although these semiconductor packages have solved a number of problems, the fabrication process to form such packages requires numerous fabrication steps and specialized equipment and materials, especially for the creation of the ball towers and the related steps providing encapsulation around the towers. Also, the required formation of multiple stacks of gold balls in the package inevitably increases the vertical size or height of the package.
In view of the foregoing limitations, there is a need in the semiconductor art for an improved method for forming semiconductor packages of compact size ("chip scale packages") having a minimal number of component parts. Specifically, there is a need for an improved method for forming chip scale packages which are adaptable to substrate surfaces having connection points of varying alignment and spacing configurations. There is a further need for an improved method for forming a chip scale package that does not significantly complicate the manufacturing or handling of the integrated circuit and which is repeatable and reliable when using traditional mass production manufacturing techniques. Preferably, the chip scale package can be formed during and simultaneously with the fabrication and assembly of the semiconductor die.